#ifndef _HCIT_USB_H
#define _HCIT_USB_H
/******************************************************************************
 * MODULE NAME:  Hcit_usb.h
 * PROJECT CODE: BlueStream
 * DESCRIPTION:  HCI usb driver for Chimera
 * AUTHOR:       zhangyansheng
 * DATE:         12 May 2008
 *
 * SOURCE CONTROL: $Id: hcit_usb.h,v 1.5 2008/11/08 07:30:06 tianwq Exp $
 *
 * NOTE TO USERS:
 *
 *
 *
 *
 ******************************************************************************/
#include "hcit_usb_config.h"

/* Define USB register addresses */
#define USB_BASE_ADDR       RDA_AHB_USB_BASE

#define M_REG_FADDR         USB_BASE_ADDR + 0
#define M_REG_POWER         USB_BASE_ADDR + 1
#define M_REG_INTRIN1       USB_BASE_ADDR + 2
#define M_REG_INTRIN2       USB_BASE_ADDR + 3
#define M_REG_INTROUT1      USB_BASE_ADDR + 4
#define M_REG_INTROUT2      USB_BASE_ADDR + 5
#define M_REG_INTRUSB       USB_BASE_ADDR + 6
#define M_REG_INTRIN1E      USB_BASE_ADDR + 7
#define M_REG_INTRIN2E      USB_BASE_ADDR + 8
#define M_REG_INTROUT1E     USB_BASE_ADDR + 9
#define M_REG_INTROUT2E     USB_BASE_ADDR + 10
#define M_REG_INTRUSBE      USB_BASE_ADDR + 11
#define M_REG_FRAME1        USB_BASE_ADDR + 12
#define M_REG_FRAME2        USB_BASE_ADDR + 13
#define M_REG_INDEX         USB_BASE_ADDR + 14

#define M_REG_CSR0          USB_BASE_ADDR + 17
#define M_REG_INMAXP        USB_BASE_ADDR + 16
#define M_REG_INCSR1        USB_BASE_ADDR + 17
#define M_REG_INCSR2        USB_BASE_ADDR + 18
#define M_REG_OUTMAXP       USB_BASE_ADDR + 19
#define M_REG_OUTCSR1       USB_BASE_ADDR + 20
#define M_REG_OUTCSR2       USB_BASE_ADDR + 21
#define M_REG_OUTCOUNT1     USB_BASE_ADDR + 22
#define M_REG_OUTCOUNT2     USB_BASE_ADDR + 23
#define M_REG_Power2        USB_BASE_ADDR + 24

#define M_FIFO_EP0          USB_BASE_ADDR + 32


/* Interrupt register bit masks */
#define M_INTR_SUSPEND          0x01
#define M_INTR_RESUME           0x02
#define M_INTR_RESET            0x04
#define M_INTR_EP0              0x0001

/* CSR0 bit masks */
#define M_CSR0_OUTPKTRDY        0x01
#define M_CSR0_INPKTRDY         0x02
#define M_CSR0_SENTSTALL        0x04
#define M_CSR0_DATAEND          0x08
#define M_CSR0_SETUPEND         0x10
#define M_CSR0_SENDSTALL        0x20
#define M_CSR0_SVDOUTPKTRDY     0x40
#define M_CSR0_SVDSETUPEND      0x80

/* Endpoint CSR register bits */
#define M_INCSR2_AutoSet        0x80
#define M_INCSR2_ISO            0x40
#define M_INCSR2_MODE           0x20
#define M_INCSR_CDT             0x40
#define M_INCSR_FF              0x08
#define M_INCSR_IPR             0x01
#define M_OUTCSR2_AutoClear     0x80
#define M_OUTCSR2_ISO           0x40
#define M_OUTCSR_CDT            0x80
#define M_OUTCSR_FF             0x10
#define M_OUTCSR_OPR            0x01


/* Register read/write macros */
#define MREAD_BYTE(addr) *((BYTE *)(addr))
#define MWRITE_BYTE(addr,data) *((BYTE *)(addr)) = data

/* Define endpoint call status values */
#define M_EP_NORMAL             0
#define M_EP_RESET              1

/* Define device states */
#define DEVSTATE_DEFAULT        0
#define DEVSTATE_ADDRESS        1
#define DEVSTATE_CONFIG         2

/* Define standard constants */
#ifndef FALSE
#define FALSE 0
#endif

#ifndef TRUE
#define TRUE  (!FALSE)
#endif

#ifndef NULL
#define NULL 0
#endif



/* Function prototypes */
void FIFORead (int, int, volatile void*);
void FIFOWrite (int, int, volatile void*);
void HCIT_Chimera_USB_DescInitialise (void);
void HCIT_Chimera_USB_EP0INT_Handler (int);
void EndpointBulkIn (PM_EPBIN_STATUS, int);
void EndpointISOIn (PM_EPBIN_STATUS, int);
void EndpointBulkOut (PM_EPBOUT_STATUS, int);
int ConfigureIfs (void);

void StdDevReq (PM_EP0_STATUS , PCOMMAND );

void HCIT_Chimera_USB_Initialise(void);
void HCIT_Chimera_USB_Interrupt_Handler(void);
int HCIT_Chimera_USB_Transmit(u_int8 *block_start,u_int32 block_length, u_int8 *header,
        unsigned int queue,t_deviceIndex device_index);


#endif /* _HCIT_USB_H */
